is their primary focus. It is not enough for a design to simply work at the typical process corner and pass layout connectivity. They consider back-annotated layout parasitic as integral to the design, and stress their circuits through extensive simulation, both at the block and top-level, to make sure they exceed their targets.

Speed is their next highest priority, both of the circuits themselves, and in the time it takes to deliver working silicon. They continuously strive to reduce design cycle time, with a track record of completely functional first silicon.