Description The Intel Xeon Phi coprocessor, the first product of Intel’s Many Integrated Core (MIC) Architecture. Location Natal, Rio Grande do Sul, Brazil Event Type Class, Conference, Seminar Regions Latin America Start Date Mar 18, 2016 End Date Mar 19, 2016 Venue Name Federal University of Rio Grande do Norte Event URL indico.ncc.unesp.br/event/19/ Registration URL Click here to register
The Intel Xeon Phi coprocessor, the first product of Intel’s Many Integrated Core (MIC) Architecture, is a new accelerator technology developed by Intel to enable performance gains for highly parallel computing workloads. It possesses several interesting and appealing features, including the ability to use familiar programming models such as OpenMP
and MPI.
The Intel Xeon Phi Coprocessor Workshop, offered by Universidade Estadual Paulista (UNESP) in partnership with Intel Brazil Software , AIMS To provide a comprehensive, practical introduction to the Xeon Phi architecture and programming models. It Has Been conceived with a special focus on the active participation of the attendees.
